(FR)Īmplificateur de puissance CMOS à tension de sortie en mode entièrement différentiel pouvant être utilisé pour une puce de mémoire rémanente en mode mixte servant à enregistrer et à reproduire la voix, et pouvant gérer une charge à très basse impédance telle qu'un haut-parleur 8 $g(V) alimenté par une source basse tension. The amplifier also includes a mechanism for crossover distortion reduction at the output driver stage, and a scheme to set the idle current in the output driver n-MOS transistors (MN7, MN9). It also utilizes native n-MOS having a threshold voltage VT = 0v for the folded cascode differential input and the source follower output stage (MN7), enhancement n-MOS (VT = 0.7v) for the common source output, and a voltage regulator (22) using p-MOS diode connected devices (M1-M5) for simulating a resistor divider to regulate the voltage multiplier output. This fully differential CMOS power amplifier utilizes a voltage multiplying technique for the input stage (MN2, MN3, MP6, MP7), a level shift/gain stage (MN/P12, MN/P13), and a common mode feedback network (MN1, MN10, MP10).

A fully differential output CMOS power amplifier suitable to be used in a non-volatile memory mixed mode chip for voice record and playback to drive a very low impedance load such as an 8-ohm speaker from a low voltage supply.

Differential output amplifier